This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined

Multi-level electronic systems offer speed and area simplicity, reducing the complexity of implementation and power dissipation. In this paper, a Hybrid ternary Full Adder (FA) is proposed using Conventional Complementary Metal Oxide Semiconductor (CCMOS), Double Pass-transistor Logic (DPL), and Pass Transistors (PT). The proposed FA is extended up to 64-bits to test scalability. To validate the proposed full adder and calculate its performance analysis, the Cadence Virtuoso toolset is used at technology 130nm with supply voltage 0.9V. An extra transistor is added to overcome the sneak path

Due to the good correlation between the physiological and pathological conditions of fruits and vegetables and their equivalent Cole impedance model parameters, an accurate and reliable technique for their identification is sought by many researchers since the introduction of the model in early 1940s. The nonlinear least squares (NLS) and its variants are examples of the conventional optimization techniques that are commonly used in literature to tackle this problem based on complex-valued impedance measurement data. However, as happens in most conventional techniques, the NLS and its variants

This paper introduces a fractional-order eardrum Type-II model, which is derived using fractional calculus to reduce the number of elements compared to its integer-order counterpart. The proposed fractional-order model parameters are extracted and compared using five meta-heuristic optimization techniques. The CMOS implementation of the model is performed using the Design Kit of the Austria Mikro Systeme (AMS) 0.35 μ m CMOS process, while the simulations have been performed using the Cadence IC design suite. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

This paper introduces a new representation of the human brain neuron cell response. Implementation of a single cell model of an excitatory and inhibitory neuron. The architecture is based on mimic the real reaction of the neuron cell. Excitatory and inhibitory are implemented in generic form for all neuron's behavior. The design is tested experimentally using FPGA. The designs have been realized, simulated using Xilinx ISE 14.7, and realized on Xilinx FPGA Virtex Artix-7 XC7A100T. The proposed realization shows good performance to be compatible with various applications. © 2020 IEEE.

This paper proposes a general prototype fractional order filter based on a two-port network concept with four external impedances. Three induced classifications from the general prototype are extracted with one, two and three external impedances, achieving ten possible generalized topologies. The external impedances are fractional-order elements and resistors. There are forty-six filters divided into twenty-two and twenty-four different general fractional filters of order “α” and order “α + β”, respectively. The general transfer functions, the necessary network conditions, and the critical

In this paper, a current-controlled fractional-order memristor model and its emulator are proposed. The emulator is built using two second generation current conveyor (CCII) and fractional-order capacitor. It is shown that the effect of the fractional order is clearly noticeable in the circuit response. PSPICE simulations are introduced for different values of the fractional order showing noticeable variations of the pinched-loop hysteresis curves. The fractional order model shows wider frequency of operation and larger pinched loop hysteresis area than the integer one. © 2017 IEEE.

This paper presents three different optimization cases for normalized fractional order low-pass filters (LPFs) with numerical, circuit and experimental results. A multi-objective optimization technique is used for controlling some filter specifications, which are the transition bandwidth, the stop band frequency gain and the maximum allowable peak in the filter pass band. The extra degree of freedom provided by the fractional order parameter allows the full manipulation of the filter specifications to obtain the desired response required by any application. The proposed mathematical model is

This paper presents a generalized form of the fractional logistic map. Two general parameters a and b are added to the classical fractional logistic equation. The effect of such parameters on the map is studied explicitly, in combination with the fractional order parameter α, which offers an extra degree of freedom increasing the design flexibility and adding more controllability on the design. The vertical and the zooming map are two special maps that arise as a result of the added parameters. Moreover, different design problems are offered in this work, as a resultant of the control of all

This paper presents the generalization of a delayed version of the logistic map. The effect of the added two general parameters is studied, which offers the option of having three different maps. The dynamic behavior of the vertical, zooming and the general map is analyzed. The study of the fixed points, stability ranges and bifurcation diagram of the delayed logistic map at hand is detailed in this work. The flow of the system behavior from stability to chaos is also presented with its transient response as well as its phase plane portraits. Moreover, using the general parameters, the option