Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modeling the effect of such an influential component has been widely studied from many perspectives. In this article, we propose a new general formula for RLC interconnect circuit model in CMOS technology using the fractional-order elements approach. The study is based on approximating an infinite transfer function of the CMOS circuit with a noninteger distributed RLC load to a finite number of poles. It is accurate due to the

In this work, a proposed circuit is implemented using tsmc 0.18um technology of area 16642 um2 with supply voltage equals 5V. A proposed implementation of a controllable Operational Transconductance Amplifier (OTA) slew rate for CMOS image sensor (CIS) is proposed. The slew rate is controlled by switching between various bias circuits for the OTA. The biasing circuit controls the value of OTA biased current, which allows controlling the amplifier's characteristics. As the flicker noise in the main contributor in reducing the quality of image sensors performance. The proposed circuit allows

This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that

Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up the multiplier operation. The proposed ALU is designed using Verilog and verified using Xilinx Virtex-5 XC5VLX30 FPGA. © 2016 IEEE.

Background: One of the major concerns in implantable optoelectronics is the heat generated by emitters such as light emitting diodes (LEDs). Such devices typically produce more heat than light, whereas medical regulations state that the surface temperature change of medical implants must stay below + 2 °C. The LED's reverse current can be employed as a temperature-sensitive parameter to measure the temperature change at the implant's surface, and thus, monitor temperature rises. The main challenge in this approach is to bias the LED with a robust voltage since the reverse current is strongly

An implementation of a fractional-order differentiator-lowpass filter is presented in this work, which is constructed from Operational Transconductance Amplifiers as active cells. This offers the benefits of electronic tuning and, also, of monolithic implementation. The presented scheme has been employed for the extraction of the R peaks in electrocardiogram signals due to its efficiency for performing this task even in a noisy environment. The provided post-layout simulation results confirm the correct operation of this solution as well as its reasonable sensitivity characteristics. © 2019

This paper presents a multiplierless based FPGA implementation for six different chaotic Pseudo Random Number Generators (PRNGs) that are based on: Chua, modified Lorenz, modified Rössler, Frequency Dependent Negative Resistor (FDNR) oscillator, and other two systems that are modelled using the simple jerk equation. These chosen systems can be employed in high speed applications because they don't utilize any hardware multiplier. The proposed PRNGs have been implemented using VHDL, synthesized on Xilinx, using the FPGA: XC5VLX50T, and tested using the NIST statistical suite. Furthermore, a

This paper presents a comparative study of edge detection algorithms based on integer and fractional order differentiation. A performance comparison of the two algorithms has been proposed. Then, a soft computing technique has been applied to both algorithms for better edge detection. From the simulations, it shows that better performance is obtained compared to the classical approach. The noise performances of those algorithms are analyzed upon the addition of random Gaussian noise, as well as the addition of salt and pepper noise. The performance has been compared to peak signal to noise

Pulsed wave Doppler ultrasound is commonly used in the diagnosis of cardiovascular and blood flow abnormalities. Doppler techniques have gained clinical significance due to its safety, real-time performance and affordability. This work presents the development of a pulsed wave spectral Doppler module, which was integrated into a reconfigurable ultrasound system. The targeted system adopts a hardware-software partitioning scheme where an FPGA handles the front-end and a PC performs the back-end. Two factors were considered during the design. First, the data transfer rate between hardware and

This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the double humped logistic map as well as the fractional order logistic map. The mixing of the map parameters and the initial conditions x0, offers a great variety for constructing more efficient encryption keys. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE