This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the transistor level. The system, which is fully automated with a universal clock signal, is tested for real time Cadence simulations using a 130nm model from which static and dynamic parameters are

A new second-order MOS transistor based circuit block approximating the behavior of a fractional-order capacitor is proposed. The circuit is modular and therefore the order of the approximation can be increased by more stages of the same circuit in cascade or in parallel. Simulation results using a TSMC 65nm CMOS technology are provided and show less than 2o of phase error in two decades around the center frequency of the approximation. Experimental results of realized fractional-order capacitors and of a fractional-order relaxation oscillator are also shown. © 2019 IEEE

Memristors are used in many innovative research areas. However, the temperature has a strong effect on mem-ristance, which results in malfunctions. Although commercial a memristor is available, its thermal characteristics are still under-explored. This paper presents a temperature model of a self-directed channel memristor. The experimental results of measuring high-resistive-state memristance between 253K and 383K show the inverse relation, which can be described by an exponential equation. This relation is similar to metal-oxide memristors; therefore, our model is expected to cover many

Multipliers are a major energy and delay contributor in modern compute-intensive applications due to their complex logic architecture. As such, designing multipliers with reduced energy and faster speed has remained a thoroughgoing challenge. This paper presents a novel, carry-free multiplier, which is suitable for a new-generation of energy-constrained applications. The multiplier circuit consists of an array of memristor-transistor cells that can be selected (i.e., turned ON or OFF) using a combination of DC bias voltages based on the operand values. When a cell is selected it contributes to

Having an approximate realization of the fractance device is an essential part of fractional-order filter design and implementation. This encouraged researchers to introduce many approximation techniques of fractional-order elements. In this paper, the fractional-order KHN low-pass and high-pass filters are investigated based on four different approximation techniques: Continued Fraction Expansion, Matsuda, Oustaloup, and Valsa. Fractional-order filter fundamentals are reviewed then a comparison is made between the ideal and actual characteristic of the filter realized with each approximation

This paper proposes a current-/voltage-controlled universal emulator that can realize any fractional-order memelements (FOME). The proposed emulator consists of second-generation current conveyors (CCII) block, two switches, and a multiplier/divider block. The first switch controls the emulator mode (voltage or current), while, the other controls the type of the emulated FOME. The influence of the fractional-order capacitor (FOC) on the pinched hysteresis loop (PHL) area, is discussed which increases the controllability on the double loop area and the working frequency range. Numerical and

Energy and clean energy are big concerns and interests. As the needs differ from area to another, different solutions appear. Energy cost, availability, reliability and trading rules are important keys in energy market. Energy sharing is a hot topic as a consumer being a part of the sustainable distributed system also making benefits such as Prosumer. Blockchain technology provides more secure, distributed and fast way to transact financial payments between clients. This paper provide a simulation case for energy sharing concept using smart contract as a tool to rule the sharing process on

Recently, fractional edge detection algorithms have gained focus of many researchers. Most of them concern on the fractional masks implementation without optimization of threshold levels of the algorithm for each image. One of the main problems of the edge detection techniques is the choice of optimal threshold for each image. In this paper, the genetic algorithm has been used to get the optimal threshold levels for each image to enhance the edge detection of the fractional masks. A fully automatic way to cluster an image using K-means principle has been applied to different fractional edge

The coming years may see the advent of distributed implantable devices to support bioelectronic medicinal treatments. Communication between implantable components and between deep implants and the outside world can be challenging. Percutaneous wired connectivity is undesirable and both radiofrequency and optical methods are limited by tissue absorption and power safety limits. As such, there is a significant potential niche for ultrasound communications in this domain. In this paper, we present the design and testing of a reliable and efficient ultrasonic communication telemetry scheme using

Wireless power transfer (WPT) has been widely employed in many applications. Its advantages have added more safety and ease in various medical, industrial, and electrical applications. This paper investigates the two-port network concept in the analysis of the fractional-Order WPT circuit. A general expression for the WPT efficiency as a function of two-port network parameters is derived. It is represented in terms of the transmission matrix parameters of a generalized Two-Port network. The analysis is performed on both Series-Series (SS) and Series-Parallel (SP) topologies. The best