This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. Performance analyses of the DS2B, including differential/linear cryptanalysis, bijective, nonlinearity, strict avalanche criterion (SAC), and bit independence criterion (BIC) have been presented where high nonlinearity , and low differential

The main goal of this work is to exploit different tools in order to approximate a general double exponent fractional-order transfer function. Through the appropriate selection of the two fractional orders of this function, different types of filters can be derived. The investigated approximation tools are either curve fitting based tools or the Padé approximation tool, and the derived approximated transfer functions in all cases have the form of rational integer-order polynomials, which can be easily realized electronically. © 2020, Springer Science+Business Media, LLC, part of Springer

The success of fractional-order fractance (FOF) as a modeling tool in (photo)bio(electro)chemical systems can be readily gauged by the large body of research work that has been conducted over the past few years in terms of materials fabrication, building integer-order emulators of their behavior, as well as applications in filter design, controller design, modeling of energy storage devices and biomaterials. The impedance of FOF has the general form Zα(s)=kαsα where kα and α are real constant and s=jω is the complex Laplace number. In this work, we investigate the possibility of decoupling the

A structure suitable for implementing power-law low-pass and high-pass filter transfer functions is presented in this work. Through the utilization of a field-programmable analog array device, full programmability of the characteristics of the intermediate stages, as is required for realizing the rational integer-order transfer function that approximates the corresponding power-law function, was achieved, making the structure versatile. In addition, a comparison between power-law and fractional-order filters regarding the effect of the non-integer order was performed. The presented design

In this paper, we report on the design of a class of analog filters based on the cascode circuit structure surrounded by four impedances. The proposed topology is systematically investigated using two-port network techniques and symbolic math CAD tools. A total of 106 second-order filter circuits can be obtained from this class including 9 low-pass filters, 6 high-pass filters, 73 bandpass filters, 6 band-stop filters, and 12 gain equalizer/all-pass filters. Post-layout simulations in 65-nm CMOS technology of selected members of this family of filters are provided and prove its correct

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 21 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to evaluate different loss components in order to find the optimal design point of highest conversion efficiency. This optimization method is verified through SPICE simulations on a 21 SC power stage in

A new clock distribution technique is introduced in this paper. The technique avoids repeaters completely and distributes the clock directly on the passive interconnect network. The wires can be highly lossy, yet the clock is delivered with a very good shape and eye. The technique uses the characteristics of the interconnect to attenuate all frequency components equally. The resulting clock at the sinks does not depend on supply variations at all and only depends on the LC time constant of the wires. Interestingly, the technique works even better with higher clock frequencies. Signal

A novel digital comparator topology is presented. The proposed digital comparator cell uses transistors' ratio to program a fixed comparison level. A double-bound hysteretic control comparator, for DC-DC converters, is built using the proposed digital comparator cell. The hysteretic-band width variation, due to process effects, decreases with increased preamplifier stage gain and constitutes a fixed ratio of the hysteretic-band width. The proposed comparator does not require offset cancellation circuits, which reduces power consumption as well as the die area and increases the comparison speed

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy of the sensor, and the second is the power consumption of the temperature sensor that needs to be reduced. A simplified counter approach is used here instead of the commonly used complex decimation filter

In this paper, a new self-timed signaling technique for reliable low-power on-chip SerDes (Serialization and DeSerialization) links is presented. The transmitter serializes 8 parallel bits at 1.5GHz, and multiplexes the 12Gbps serial data stream with a 24GHz clock on a single line using three level signaling. This new signaling technique enables the receiver to recover the clock from the data with a simple phase detector circuitry. Moreover, this technique is insensitive to jitter accumulated during signal propagation or at the receiver input because the clock signal is extracted from the