This paper proposes a speech encryption scheme based on a generalized modified chaotic tent map and bit permutation and presents its hardware realization. The generalization scales the output range and increases the key space. The modification controls the bounds on the output range through a parameter such that chaotic output exists for almost all values of the parameter. The security and efficiency of the speech encryption scheme are validated through the randomness of the encrypted signal, the key sensitivity and the hardware resources utilization. The proposed scheme utilizes less FPGA

Chaotic systems generating multi-wing attractors have received considerable attention in the literature. In this work, we propose a novel three-dimensional chaotic system with hyperbolic sine nonlinearity. It is worth noting that the system is elegant and includes only one parameter. Despite its simple structure, the new system displays double-wing and four-wing chaotic attractors. By studying dynamics of the system, coexistence of limit cycles or chaotic attractors is discovered. The capable of the synchronization of new chaotic system is verified by using an adaptive control. Furthermore, an

This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB

Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, configurable and low power Viterbi decoder for

Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reconfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for

In this study, we show that the discharge voltage pattern of a supercapacitor exhibiting fractional-order behavior from the same initial steady-state voltage into a constant resistor is dependent on the past charging voltage profile. The charging voltage was designed to follow a power-law function, i.e. [Formula: see text], in which [Formula: see text] (charging time duration between zero voltage to the terminal voltage [Formula: see text]) and p ([Formula: see text]) act as two variable parameters. We used this history-dependence of the dynamic behavior of the device to uniquely retrieve

A simple realization of the fractional-order Mihalas-Niebur neuron model is presented in this work. The required low-pass filter is implemented using current-mirrors offering simple circuitry and, also, electronic tunability of the realized time-constant. Due to the limited bandwidth required for this application, the necessary fractional-order capacitor is realized using an appropriately configured second-order RC network. The proposed realization highlights the connection between the fractional-order and the frequency spiking of the model through appropriate simulation results, which are

In this paper the variability of supercapacitor fractional-order model parameters are explored when extracted using a non-linear least squares optimization applied to their constant current discharging behaviour. The variability of parameters extracted 1000 different times applying the optimization process to multiple sets of simulated and experimental data are presented to validate this approach. The experimental results were collected from 4 samples of Panasonic EEC-SSR5H105 supercapacitors (1 F rating) acting as a secondary power source for an Arduino Uno system. Simulations using the

A few special chaotic systems without unstable equilibrium points have been investigated recently. It is worth noting that these special systems are different from normal chaotic ones because the classical Shilnikov criterion cannot be used to prove chaos of such systems. A novel unusual chaotic system without equilibrium is proposed in this work. We discover dynamical properties as well as the synchronization of the new system. Furthermore, a physical realization of the system without equilibrium is also implemented to illustrate its feasibility. © 2017 Ahmad Taher Azar et al.

This paper discusses the influence of the fractional order parameter on conventional chaotic systems. These fractional-order parameters increase the system degree of freedom allowing it to enter new domains and thus it can be used as a control for such dynamical systems. This paper investigates the behaviour of the equally-fractional-order Lü chaotic system when changing the fractional-order parameter and determines the fractional-order ranges for chaotic behaviour. Five different parameter values and six fractional-order cases are discussed through this paper. Unlike the conventional