This paper introduces some generalized fundamentals for fractional-order RL β C α circuits as well as a gradient-based optimization technique in the frequency domain. One of the main advantages of the fractional-order design is that it increases the flexibility and degrees of freedom by means of the fractional parameters, which provide new fundamentals and can be used for better interpretation or best fit matching with experimental results. An analysis of the real and imaginary components, the magnitude and phase responses, and the sensitivity must be performed to obtain an optimal design

Nonlinear dynamical systems with chaotic attractors have many engineering applications such as dynamical models or pseudo-random number generators. Discovering systems with hidden attractors has recently received considerable attention because they can lead to unexpected responses to perturbations. In this chapter, several recent examples of hidden attractors, which are classified into several categories from two different viewpoints, are reviewed. From the viewpoint of the equilibrium type, they are classified into systems with no equilibria, with a line of equilibrium points, and with one

Chaotic systems appear in many applications such as pseudo-random number generation, text encryption, and secure image transfer. Numerical solutions of these systems using digital software or hardware inevitably deviate from the expected analytical solutions. Chaotic orbits produced using finite precision systems do not exhibit the infinite period expected under the assumptions of infinite simulation time and precision. In this paper, digital implementation of the generalized logisticmap with signed parameter is considered. We present a fixed-point hardware realization of a Pseudo-Random

The electric characteristics of electric-double layer capacitors (EDLCs) are determined by their capacitance which is usually measured in the time domain from constant-current charging/discharging and cyclic voltammetry tests, and from the frequency domain using nonlinear least-squares fitting of spectral impedance. The time-voltage and current-voltage profiles from the first two techniques are commonly treated by assuming ideal S s C behavior in spite of the nonlinear response of the device, which in turn provides inaccurate values for its characteristic metrics. In this paper we revisit the

Multi-phase oscillator is an essential block in digital communication systems especially phase shift keying PSK based systems. In this paper, a procedure for designing a multi-phase oscillator with any required phase shift is proposed, unlike the previous oscillator which generates equal phase shifts. This oscillator circuit is built using fractional-order elements to generate any distribution of phase shift. The general characteristics equation is studied where the condition for oscillation and oscillation frequency are derived. Finally, different examples are introduced with their

A novel low dropout (LDO) voltage regulator compensation technique is demonstrated. A parallel feedback path is used to insert a zero at approximately three times the output pole. The parallel feedback consists of passive elements only and occupies small area. The proposed technique completely eliminates the output pole at different load conditions and results in high LDO bandwidth, which achieves fast output tracking of the input reference and fast recovery of sudden load changes. Moreover, the output pole elimination at different load conditions enables the potential scaling of the error

This paper proposes a generalized modified chaotic transition map with three independent parameters. A hardware speech encryption scheme utilizing this map along with a bit permutation network is presented. While the transition map’s generalization introduces additional parameters, the modification enhances its chaotic properties and overcomes the finite range of the control parameter and dynamical degradation problems. The modification also presents a simplification for the hardware realization of the exponentiation operation in the map’s equation because the modified output range allows

This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and

This paper proposes a speech encryption scheme based on a generalized modified chaotic tent map and bit permutation and presents its hardware realization. The generalization scales the output range and increases the key space. The modification controls the bounds on the output range through a parameter such that chaotic output exists for almost all values of the parameter. The security and efficiency of the speech encryption scheme are validated through the randomness of the encrypted signal, the key sensitivity and the hardware resources utilization. The proposed scheme utilizes less FPGA

Chaotic systems generating multi-wing attractors have received considerable attention in the literature. In this work, we propose a novel three-dimensional chaotic system with hyperbolic sine nonlinearity. It is worth noting that the system is elegant and includes only one parameter. Despite its simple structure, the new system displays double-wing and four-wing chaotic attractors. By studying dynamics of the system, coexistence of limit cycles or chaotic attractors is discovered. The capable of the synchronization of new chaotic system is verified by using an adaptive control. Furthermore, an