In this paper, a new scheme for the realization of an optical logic circuit using Mach–Zehnder modulators (MZM) with direct detection has been proposed. Amplitude and phase information of the optical signals have been used for the differentiation of optical signals into four different states that can be represented using two binary inputs, while direct detection has been used for the effective mapping of these states with their respective binary outputs. The realization of seven logic gates, two reversible optical logic gates (Feynman and double Feynman gates) and half adder and half

Modularity concepts attracted the attention of many researchers as it plays an important role in product design problems. Modularity requires dividing a product into a set of modules that are independent between each other and dependent within. The product is represented using Design Structure Matrix (DSM). DSM works as a system representation tool; it visualizes the interrelationship between product elements. In this research, a comparison is conducted between four optimization algorithms: Emperor Penguins Colony (EPC), First Modified Emperor Penguins Colony (MEPC1), Second Modified Emperor

Genetic algorithms (GAs) are intended to look for the optimum solution by eliminating the gene strings with the worst fitness. Hence, this paper proposes an optimized edge detection technique based on a genetic algorithm. A training dataset that consists of simple images and their corresponding optimal edge features is employed to obtain the optimum filter coefficients along with the optimum thresholding algorithm. Qualitative and quantitative performance analyses are investigated based on several well-known metrics. The performance of the proposed genetic algorithm-based cost minimization

A differentiator-based set up is proposed as an alternative solution to measure bio-impedance. The method is modifying the differentiator circuit, replacing the capacitor with the Cole-impedance model representing the biological (fruit) sample. The proposed differentiator gain response (with the embedded fruit) is experimentally recorded. The experimental data’s post-processing is performed using meta-heuristic optimization techniques to extract the Cole-impedance model unknown parameters by solving a group of nonlinear equations. Three meta-heuristic optimization algorithms are used: the moth

Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is

Chaotic systems have remarkable importance in capturing some complex features of the physical process. Recently, fractional calculus becomes a vigorous tool in characterizing the dynamics of complex systems. The fractional-order chaotic systems increase the chaotic behavior in new dimensions and add extra degrees of freedom, which increase system controllability. In this chapter, FPGA implementation of different integer and fractional-order chaotic systems is presented. The investigated integer-order systems include Chua double scroll chaotic system and the modified Chua N-scroll chaotic

Product integration (PI) rules are well known numerical techniques that are used to solve differential equations of integer and, recently, fractional orders. Due to the high memory dependency of the PI rules used in solving fractional-order systems (FOS), their hardware implementation is very difficult and resources-demanding. In this paper, modified versions of the PI rules are introduced to facilitate their digital implementations. The studied rules are PI rectangular, PI trapezoidal, and predict-evaluate-correct-evaluate (PECE) rules. The three modified versions of the PI rules are

This paper introduces design and FPGA implementation of sound encryption system based on a fractional-order chaotic system. Also, it presents the FPGA implementation of Tang, Yalcin, and Özoǧuz fractional order chaotic systems. The Grunwald-Letnikov (GL) definition is used to generalize the investigated systems into the fractional-order domain. Also, the variation of parameters for each system is investigated against the window size of the GL definition. Xilinx ISE 14.5 is used to simulate the proposed design. Also, some hardware reduction techniques are applied to decrease hardware

This paper proposes FPGA realization of an IP core for generic fractional-order derivative based on Grünwald-Letnikov approximation. This generic design is applied to achieve reconfigurable realization of fractional-order chaotic systems. The fractional-order real-time configuration boosts the suitability of this particular realization for different applications, including dynamic switching, synchronization, and encryption. The proposed design targets optimized utilization of the FPGA internal resources and efficient employment of the external peripherals: switches and I/O ports in the FPGA

The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter