Empirical Temperature Model of Self-Directed Channel Memristor
Memristors are used in many innovative research areas. However, the temperature has a strong effect on mem-ristance, which results in malfunctions. Although commercial a memristor is available, its thermal characteristics are still under-explored. This paper presents a temperature model of a self-directed channel memristor. The experimental results of measuring high-resistive-state memristance between 253K and 383K show the inverse relation, which can be described by an exponential equation. This relation is similar to metal-oxide memristors; therefore, our model is expected to cover many
Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture
Multipliers are a major energy and delay contributor in modern compute-intensive applications due to their complex logic architecture. As such, designing multipliers with reduced energy and faster speed has remained a thoroughgoing challenge. This paper presents a novel, carry-free multiplier, which is suitable for a new-generation of energy-constrained applications. The multiplier circuit consists of an array of memristor-transistor cells that can be selected (i.e., turned ON or OFF) using a combination of DC bias voltages based on the operand values. When a cell is selected it contributes to
Effect of Different Approximation Techniques on Fractional-Order KHN Filter Design
Having an approximate realization of the fractance device is an essential part of fractional-order filter design and implementation. This encouraged researchers to introduce many approximation techniques of fractional-order elements. In this paper, the fractional-order KHN low-pass and high-pass filters are investigated based on four different approximation techniques: Continued Fraction Expansion, Matsuda, Oustaloup, and Valsa. Fractional-order filter fundamentals are reviewed then a comparison is made between the ideal and actual characteristic of the filter realized with each approximation
A Universal Fractional-Order Memelement Emulation Circuit
This paper proposes a current-/voltage-controlled universal emulator that can realize any fractional-order memelements (FOME). The proposed emulator consists of second-generation current conveyors (CCII) block, two switches, and a multiplier/divider block. The first switch controls the emulator mode (voltage or current), while, the other controls the type of the emulated FOME. The influence of the fractional-order capacitor (FOC) on the pinched hysteresis loop (PHL) area, is discussed which increases the controllability on the double loop area and the working frequency range. Numerical and
Energy Trading Based on Smart Contract Blockchain Application
Energy and clean energy are big concerns and interests. As the needs differ from area to another, different solutions appear. Energy cost, availability, reliability and trading rules are important keys in energy market. Energy sharing is a hot topic as a consumer being a part of the sustainable distributed system also making benefits such as Prosumer. Blockchain technology provides more secure, distributed and fast way to transact financial payments between clients. This paper provide a simulation case for energy sharing concept using smart contract as a tool to rule the sharing process on
Radiographic images fractional edge detection based on genetic algorithm
Recently, fractional edge detection algorithms have gained focus of many researchers. Most of them concern on the fractional masks implementation without optimization of threshold levels of the algorithm for each image. One of the main problems of the edge detection techniques is the choice of optimal threshold for each image. In this paper, the genetic algorithm has been used to get the optimal threshold levels for each image to enhance the edge detection of the fractional masks. A fully automatic way to cluster an image using K-means principle has been applied to different fractional edge
Ultrasound intra body multi node communication system for bioelectronic medicine
The coming years may see the advent of distributed implantable devices to support bioelectronic medicinal treatments. Communication between implantable components and between deep implants and the outside world can be challenging. Percutaneous wired connectivity is undesirable and both radiofrequency and optical methods are limited by tissue absorption and power safety limits. As such, there is a significant potential niche for ultrasound communications in this domain. In this paper, we present the design and testing of a reliable and efficient ultrasonic communication telemetry scheme using
Two-Port Network Analysis of Equal Fractional-order Wireless Power Transfer Circuit
Wireless power transfer (WPT) has been widely employed in many applications. Its advantages have added more safety and ease in various medical, industrial, and electrical applications. This paper investigates the two-port network concept in the analysis of the fractional-Order WPT circuit. A general expression for the WPT efficiency as a function of two-port network parameters is derived. It is represented in terms of the transmission matrix parameters of a generalized Two-Port network. The analysis is performed on both Series-Series (SS) and Series-Parallel (SP) topologies. The best
Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements
Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modeling the effect of such an influential component has been widely studied from many perspectives. In this article, we propose a new general formula for RLC interconnect circuit model in CMOS technology using the fractional-order elements approach. The study is based on approximating an infinite transfer function of the CMOS circuit with a noninteger distributed RLC load to a finite number of poles. It is accurate due to the
Controllable OTA Slew-rate for CMOS Image Sensor
In this work, a proposed circuit is implemented using tsmc 0.18um technology of area 16642 um2 with supply voltage equals 5V. A proposed implementation of a controllable Operational Transconductance Amplifier (OTA) slew rate for CMOS image sensor (CIS) is proposed. The slew rate is controlled by switching between various bias circuits for the OTA. The biasing circuit controls the value of OTA biased current, which allows controlling the amplifier's characteristics. As the flicker noise in the main contributor in reducing the quality of image sensors performance. The proposed circuit allows
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