In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70 *70 m 2. The phase noise of the free running DCO is 92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency. © 2011 IEEE.

A novel technique to remove the slow-switching-limit (SSL) loss in switched-capacitor (SC) dc-dc converters is presented. A small series inductor is cascaded with an SC converter causing adiabatic charging of the converter's energy-transfer capacitors. In this work, the theory and necessary conditions for SSL loss elimination through an inductive output filter are derived. The new topology enables high efficiency for on-die dc-dc converters while maintaining reasonable energy density. A 2:1 SC converter is built in 65-nm CMOS process to validate the analysis methods and asses the proposed

In this paper, a new self-timed signaling technique for reliable low-power on-chip SerDes (Serialization and DeSerialization) links is presented. The transmitter serializes 8 parallel bits at 1.5GHz, and multiplexes the 12Gbps serial data stream with a 24GHz clock on a single line using three level signaling. This new signaling technique enables the receiver to recover the clock from the data with a simple phase detector circuitry. Moreover, this technique is insensitive to jitter accumulated during signal propagation or at the receiver input because the clock signal is extracted from the

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy of the sensor, and the second is the power consumption of the temperature sensor that needs to be reduced. A simplified counter approach is used here instead of the commonly used complex decimation filter

A novel digital comparator topology is presented. The proposed digital comparator cell uses transistors' ratio to program a fixed comparison level. A double-bound hysteretic control comparator, for DC-DC converters, is built using the proposed digital comparator cell. The hysteretic-band width variation, due to process effects, decreases with increased preamplifier stage gain and constitutes a fixed ratio of the hysteretic-band width. The proposed comparator does not require offset cancellation circuits, which reduces power consumption as well as the die area and increases the comparison speed

A new clock distribution technique is introduced in this paper. The technique avoids repeaters completely and distributes the clock directly on the passive interconnect network. The wires can be highly lossy, yet the clock is delivered with a very good shape and eye. The technique uses the characteristics of the interconnect to attenuate all frequency components equally. The resulting clock at the sinks does not depend on supply variations at all and only depends on the LC time constant of the wires. Interestingly, the technique works even better with higher clock frequencies. Signal

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 21 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to evaluate different loss components in order to find the optimal design point of highest conversion efficiency. This optimization method is verified through SPICE simulations on a 21 SC power stage in

In this paper, we report on the design of a class of analog filters based on the cascode circuit structure surrounded by four impedances. The proposed topology is systematically investigated using two-port network techniques and symbolic math CAD tools. A total of 106 second-order filter circuits can be obtained from this class including 9 low-pass filters, 6 high-pass filters, 73 bandpass filters, 6 band-stop filters, and 12 gain equalizer/all-pass filters. Post-layout simulations in 65-nm CMOS technology of selected members of this family of filters are provided and prove its correct

A structure suitable for implementing power-law low-pass and high-pass filter transfer functions is presented in this work. Through the utilization of a field-programmable analog array device, full programmability of the characteristics of the intermediate stages, as is required for realizing the rational integer-order transfer function that approximates the corresponding power-law function, was achieved, making the structure versatile. In addition, a comparison between power-law and fractional-order filters regarding the effect of the non-integer order was performed. The presented design

The success of fractional-order fractance (FOF) as a modeling tool in (photo)bio(electro)chemical systems can be readily gauged by the large body of research work that has been conducted over the past few years in terms of materials fabrication, building integer-order emulators of their behavior, as well as applications in filter design, controller design, modeling of energy storage devices and biomaterials. The impedance of FOF has the general form Zα(s)=kαsα where kα and α are real constant and s=jω is the complex Laplace number. In this work, we investigate the possibility of decoupling the