Large and complex system-on-chip devices consisting of many processor cores, accelerators, DSP functions and many other processing and memory elements are becoming common in the semiconductor industry nowadays. To communicate, these processing and memory elements need to have a network-on-chip (NoC) that is scalable enough to support large number of elements and large bandwidth among other requirements. This paper evaluates the performance of the 2D memory-centric NoC architecture from throughput and latency perspective versus the Mesh topology. We also propose a memory-centric architecture

Mixing carbon-based materials with pseudocapacitive material is a widely used strategy to prepare high-energy, high-power supercapacitors. However, phase separation is inevitable after extended charging/discharging which leads to the degradation of performance metrics of the device. Here, we prepare in a single step cobalt-incorporated carbon nanofibers (CNF) by electrospinning homogeneous solutions of polyacrylonitrile (PAN) with cobalt acetate at different nominal proportions (1:0 to 1:1), and investigate their stability and capacitive behavior in symmetric supercapacitors. The

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To understand the physical process involved in film evaporation, a new numerical model is created using coupled quadratic finite element formulation of the conservation equations. The heat transport equation is solved in the three different phases (solid, liquid and vapor) while the Navier-Stokes equation are solved in the two fluids. The gradient discontinuity at the liquid vapor interface provides local value of the evaporative flux density that is directly linked to the interface velocity jump through mass conservation principle and used as boundary condition for two fluid flow computations

As on-chip integration increases, the thermal distribution becomes spatially non-uniform and varies based on the power dissipation. In this paper, we introduce a temperature-aware task-mapping algorithm to prevent hotspots and achieve a highly uniform thermal distribution using adaptive multi-threshold values. The algorithm monitors the temperature of the cores, swaps tasks when the temperature of the core is relatively higher than the average temperature of the chip. Cores are switched off if they exceed an absolute maximum temperature. Using this algorithm, reliability is enhanced by

This paper introduces the replacement of four and six resistors with four and six memristors at the same time for the modified single input Op-Amps oscillator. The full independency between the oscillation condition and the oscillation frequency facilitates the study. Mathematical analysis is provided for the double replacement of resistors with memristors. The whole range of operation of the memristor is taken in consideration and examined for all kind of replacements. Also, the poles of the system are presented while the existence of two, four and six memristors. © 2014 IEEE.

In this work, a generic impedance modeling technique is proposed. The technique is able to identify a circuit model that is most suitable for fitting measured impedance magnitude data using a genetic algorithm solver as well as the optimum circuit model parameters. Experimentally measured and simulated data sets with different noise levels are used to validate the technique. © 2020 Elsevier GmbH

A dynamic model of Photo-Voltaic (PV) solar module is important when it is utilized in conjunction with switching circuits and in grid connected applications. In this paper, a fractional-order dynamical model of a PV source is introduced. The model includes both a fractional series inductor and a parallel capacitor which are in general of two different orders allowing for extra degrees of modeling freedom. An expression for the load current is derived and the step response is investigated for different orders. It is found that the nature of the connections has a dominant effect on the response

Recently, the triple-lobe behavior is found in the I-V characteristics of some memristive devices generating another non-zero pinchoff point. In this paper, a flux-controlled memristive model is developed to generate the triple-lobe behavior (double pinchoff points) based on a fractional second-order model. The conditions for observing triple lobes are derived besides the coordinates of the pinchoff points. Different scenarios have been considered by changing the model parameters and fractional order. Furthermore, the minimum and maximum achievable conductances are analyzed and mathematically

A novel resistorless topology for implementing fractional-order capacitor emulators, based on the employment of Operational Transconductance Amplifiers (OTAs) as active elements, is presented in this paper. The benefits of this topology are its simplicity in terms of component count, compared to other existing topologies in the literature, in addition to its electronic tunability. The performance of the presented topology is evaluated using Cadence and the 0.35 μm CMOS process Design Kit from Austria Mikro Systeme. Experimental results using commercial OTA chips are also provided, where the